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preliminary datasheet r1ex25002asa00g/r1ex25004asa00g R1EX25002ATA00G/r1ex25004ata00g serial peripheral interface 2k eeprom (256-word ? 8-bit) 4k eeprom (512-word ? 8-bit) r10 ds0034ej0100 rev.1.00 feb. 25, 2013 105 ? c spi-bus eeprom description r1ex25xxx series is the serial pe ripheral interface compatible (spi) eeprom (electrically erasable and programmable rom). r1ex25xxxg series improves the write/e rase endurance in addition to suitable for the high temperature industrial applica tion that makes the best use of the feature of advanced monos memory cell structure. features ? single supply: 1.8 v to 5.5 v ? serial peripheral interface compatible (spi bus) ? spi mode 0 (0,0), 3 (1,1) ? clock frequency: 5 mhz (2.5 v to 5.5 v), 3 mhz (1.8 v to 5.5 v) ? power dissipation: ? standby: 2 ? a (max) ? active (read): 2 ma (max) ? active (write): 2.5 ma (max) ? automatic page write: 16-byte/page ? write cycle time: 5 ms ? endurance: 1,000k cycles @85 ? c / 200k cycles @105 ? c ? data retention: 20 years ? small size packages: sop-8pin, tssop-8pin ? shipping tape and reel ? tssop-8pin: 3,000 ic/reel ? sop-8pin : 2,500 ic/reel ? temperature range: ? 40 to ? 105 ? c ? lead free product. ? halogen free products. preliminary: the specifications of this device are subject to ch ange without notice. please contact your nearest renesa s electronics? sales dept. regarding specifications. r10ds0034ej0100 rev.1.00 page 1 of 20 feb. 25, 2013
r1ex25002asa00g/r1ex25004asa00g/R1EX25002ATA00G/r1ex25004ata00g ordering information orderable part numbers internal organization package shipping tape and reel r1ex25002asa00g#u0 2k bit (256 ? 8-bit) r1ex25004asa00g#u0 4k bit (512 ? 8-bit) 150 mil 8-pin plastic sop prsp0008df-b (fp-8dbv) lead free, halogen free 2,500 ic/reel R1EX25002ATA00G#u0 2k bit (256 ? 8-bit) r1ex25004ata00g#u0 4k bit (512 ? 8-bit) 8-pin plastic tssop ptsp0008jc-b (ttp-8dav) lead free, halogen free 3,000 ic/reel pin arrangement 8-pin sop/tssop (top view) 1 2 3 4 8 7 6 5 v cc hold c d s q w v ss pin description pin name function c serial clock d serial data input q serial data output s chip select w write protect hold hold v cc supply voltage v ss ground r10ds0034ej0100 rev.1.00 page 2 of 20 feb. 25, 2013
r1ex25002asa00g/r1ex25004asa00g/R1EX25002ATA00G/r1ex25004ata00g block diagram high voltage generator memory array y-select & sense amp. serial-parallel converter address generator control logic y decoder x decoder v cc v ss s w c hold d q voltage detector absolute maximum ratings parameter symbol value unit supply voltage relative to v ss v cc ? 0.6 to + 7.0 v input voltage relative to v ss vin ? 0.5 * 2 to +7.0 v operating temperature range * 1 topr ? 40 to +105 ?c storage temperature range tstg ? 55 to +125 ?c notes: 1. including electrical c haracteristics and data retention. 2. vin (min): ? 3.0 v for pulse width ? 50 ns. dc operating conditions parameter symbol min typ max unit supply voltage v cc 1.8 ? 5.5 v v ss 0 0 0 v input voltage v ih v cc ? 0.7 ? v cc ? 0.5 * 2 v v il ? 0.3 * 1 ? v cc ? 0.3 v operating temperat ure range topr ? 40 ? ? 105 ?c notes: 1. v il (min): ? 1.0 v for pulse width ? 50 ns. 2. v ih (max): v cc + 1.0 v for pulse width ? 50 ns. capacitance (ta = +25 ? c, f = 1 mhz) parameter symbol min typ max unit test conditions input capacitance (d,c, s , w ,hold ) cin * 1 ? ? 6.0 pf vin = 0 v output capacitance (q) c i/o * 1 ? ? 8.0 pf vout = 0 v note: 1. not 100 ? tested. memory cell characteristics (v cc = 1.8 v to 5.5 v) ta=85 ?c ta=105?c notes endurance 1,000k cycles min. 200k cycles min. 1 data retention 20 years min. 20 years min. 1 note: 1. not 100 ? tested. r10ds0034ej0100 rev.1.00 page 3 of 20 feb. 25, 2013
r1ex25002asa00g/r1ex25004asa00g/R1EX25002ATA00G/r1ex25004ata00g r10ds0034ej0100 rev.1.00 page 4 of 20 feb. 25, 2013 dc characteristics parameter symbol min typ max unit test conditions input leakage current i li ? ? 2 ? a v cc = 5.5 v, v in = 0 to 5.5 v (s, d, c, hold , w ) output leakage current i lo ? ? 2 ? a v cc = 5.5 v, v out = 0 to 5.5 v (q) v cc current standby i sb ? 0.5 ? ? a v in = v ss or v cc , v cc = 3.6 v ? ? 2 ? a v in = v ss or v cc , v cc = 5.5 v active i cc1 ? 0.2 2 ma v cc = 3.6 v, read at 5 mhz v in = v cc ? 0.1/v cc ? 0.9 q = open ? ? 2.5 ma v cc = 5.5 v, read at 5 mhz v in = v cc ? 0.1/v cc ? 0.9 q = open i cc2 ? 1.0 2 ma v cc = 3.6 v, write at 5 mhz v in = v cc ? 0.1/v cc ? 0.9 ? ? 3 ma v cc = 5.5 v, write at 5 mhz v in = v cc ? 0.1/v cc ? 0.9 output voltage v ol1 ? ? 0.4 v v cc = 5.5 v, i ol = 2 ma v ol2 ? ? 0.4 v v cc = 2.5 v, i ol = 1.5 ma v oh1 v cc ? 0.8 ? ? v v cc = 5.5 v, i oh = ? 2 ma v oh2 v cc ? 0.8 ? ? v v cc = 2.5 v, i oh = ? 0.4 ma
r1ex25002asa00g/r1ex25004asa00g/R1EX25002ATA00G/r1ex25004ata00g r10ds0034ej0100 rev.1.00 page 5 of 20 feb. 25, 2013 ac characteristics test conditions ? input pules levels: ? v il = v cc ? 0.2 ? v ih = v cc ? 0.8 ? input rise and fall time: ? 10 ns ? input and output timing reference levels: v cc ? 0.3, v cc ? 0.7 ? output reference levels: v cc ? 0.5 ? output load: 100 pf (ta = ? 40 to ? 105 ? c, v cc = 2.5 v to 5.5 v) parameter symbol alt min max unit notes clock frequency f c f sck ? 5 mhz s active setup time t slch t css1 90 ? ns s not active setup time t shch t css2 90 ? ns s deselect time t shsl t cs 90 ? ns s active hold time t chsh t csh 90 ? ns s not active hold time t chsl ? 90 ? ns clock high time t ch t clh 90 ? ns 1 clock low time t cl t cll 90 ? ns 1 clock rise time t clch t rc ? 1 ? s 2 clock fall time t chcl t fc ? 1 ? s 2 data in setup time t dvch t dsu 20 ? ns data in hold time t chdx t dh 30 ? ns clock low hold time after hold not active t hhch ? 70 ? ns clock low hold time after hold active t hlch ? 40 ? ns clock high setup time before hold active t chhl ? 60 ? ns clock high setup time before hold not active t chhh ? 60 ? ns output disable time t shqz t dis ? 100 ns 2 clock low to output valid t clqv t v ? 70 ns output hold time t clqx t ho 0 ? ns output rise time t qlqh t ro ? 50 ns 2 output fall time t qhql t fo ? 50 ns 2 hold high to output low-z t hhqx t lz ? 50 ns 2 hold low to output high-z t hlqz t hz ? 100 ns 2 write time t w t wc ? 5 ms notes: 1. t ch ? t cl ? 1/f c 2. not 100 ? tested.
r1ex25002asa00g/r1ex25004asa00g/R1EX25002ATA00G/r1ex25004ata00g r10ds0034ej0100 rev.1.00 page 6 of 20 feb. 25, 2013 (ta = ? 40 to ? 105 ? c, v cc = 1.8 v to 5.5 v) parameter symbol alt min max unit notes clock frequency f c f sck ? 3 mhz s active setup time t slch t css1 100 ? ns s not active setup time t shch t css2 100 ? ns s deselect time t shsl t cs 150 ? ns s active hold time t chsh t csh 100 ? ns s not active hold time t chsl ? 100 ? ns clock high time t ch t clh 150 ? ns 1 clock low time t cl t cll 150 ? ns 1 clock rise time t clch t rc ? 1 ? s 2 clock fall time t chcl t fc ? 1 ? s 2 data in setup time t dvch t dsu 30 ? ns data in hold time t chdx t dh 50 ? ns clock low hold time after hold not active t hhch ? 140 ? ns clock low hold time after hold active t hlch ? 90 ? ns clock high setup time before hold active t chhl ? 120 ? ns clock high setup time before hold not active t chhh ? 120 ? ns output disable time t shqz t dis ? 200 ns 2 clock low to output valid t clqv t v ? 120 ns output hold time t clqx t ho 0 ? ns output rise time t qlqh t ro ? 100 ns 2 output fall time t qhql t fo ? 100 ns 2 hold high to output low-z t hhqx t lz ? 100 ns 2 hold low to output high-z t hlqz t hz ? 100 ns 2 write time t w t wc ? 5 ms notes: 1. t ch ? t cl ? 1/f c 2. not 100 ? tested.
r1ex25002asa00g/r1ex25004asa00g/R1EX25002ATA00G/r1ex25004ata00g timing waveforms serial input timing s c t chsl t slch t chdx t clch t chcl t shch t chsh t shsl t dvch msb in lsb in d q high impedance hold timing t chhl s hold c d q t hlch t chhh t hlqz t hhqx t hhch output timing s c d q lsb out addr lsb in t qlqh t qhql t shqz t ch t cl t clqv t clqx t clqv t clqx r10ds0034ej0100 rev.1.00 page 7 of 20 feb. 25, 2013
r1ex25002asa00g/r1ex25004asa00g/R1EX25002ATA00G/r1ex25004ata00g r10ds0034ej0100 rev.1.00 page 8 of 20 feb. 25, 2013 pin function serial data output (q) this output signal is used to transfer data serially out of the device. data is shifted out on the falling edge of serial clock (c). serial data input (d) this input signal is used to transfer data serially into the device. it receives in structions, addresses, and the data to be written. values are latched on the rising edge of serial clock (c). serial clock (c) this input signal provides the timing of the serial interface. in structions, addresses, or data present at serial data input (d) are latched on the rising edge of serial clock (c). data on serial data output (q) changes after the falling edge of serial clock (c). chip select ( s ) when this input signal is high, the device is deselected and serial data output (q) is at high impedance. unless an internal write cycle is in progress, the device will be in the standby mode. driving chip select ( s ) low enables the device, placing it in the active power mode. after power-up, a falling edge on chip select ( s ) is required prior to the start of any instruction. hold ( hold ) the hold ( hold ) signal is used to pause any serial communications with the device without deselecting the device. during the hold condition, the serial data output (q) is high im pedance, and serial data input (d) and serial clock (c) are don?t care. to start the hold condition, the de vice must be selected, with chip select ( s ) driven low. write protect ( w ) this input signal is used to protect the memory against write instructions. when write protect ( w ) is held low, write instructions (wrsr, write) are ignored. no action on this signal can interrupt a write cy cle that has already started.
r1ex25002asa00g/r1ex25004asa00g/R1EX25002ATA00G/r1ex25004ata00g functional description status register the following figure shows the status re gister format. the status register contains a number of status and control bits that can be read or set (as ap propriate) by speci fic instructions. status register format 1 1 1 1 bp1 bp0 wel wip block protect bits write enable latch bits write in progress bits b0 b7 wip bit: the write in progress (wip) bit indicates whether th e memory is busy with a write or write status register cycle. wel bit: the write enable latch (wel) bit indicates the status of the internal write enable latch. bp1, bp0 bits: the block protect (bp1, bp0) bits are non- volatile. they define the size of the area to be protected against write instructions. instructions each i nstruction starts with a single-byte code, as summarized in the following table . if an invalid instruction is sent (one not contained in the following table), the device automatically deselects itself. instruction set instruction description instruction format wren write enable 0000 ? 110 wrdi write disable 0000 ? 100 rdsr read status register 0000 ? 101 wrsr write status register 0000 ? 001 read read from memory array 0000 a011 write write to memory array 0000 a010 notes: 1. ? ? ? is don?t care. 2. ?a? is a 8 address on the r1ex25004a, and don?t care on the r1ex25002a. r10ds0034ej0100 rev.1.00 page 9 of 20 feb. 25, 2013
r1ex25002asa00g/r1ex25004asa00g/R1EX25002ATA00G/r1ex25004ata00g write enable (wren): the write enable latch (wel) bit must be set prior to each write and wrsr instruction. the only way to do this is to send a write enable instruction to the device. as shown in the following figure, to send th is instruction to the device, chip select ( s ) is driven low, and the bits of the instruction byte ar e shifted in, on serial data input (d). the device then enters a wait state. it waits for the de vice to be deselected, by chip select ( s ) being driven high. write enable (wren) sequence s w c d q instruction 0123456 high-z v ih v il v ih v il v ih v il v ih v il 7 r10ds0034ej0100 rev.1.00 page 10 of 20 feb. 25, 2013
r1ex25002asa00g/r1ex25004asa00g/R1EX25002ATA00G/r1ex25004ata00g write disable (wrdi): one way of resetting the write enable latch (wel) bit is to send a write disable instruction to the device. as shown in the following figure, to send this instruction to the device, chip select ( s ) is driven low, and the bits of the instruction byte are shifted in, on serial data input (d). the device then enters a wait state. it waits fo r the device to be deselected, by chip select ( s ) being driven high. the write enable latch (wel) bit, in fact, beco mes reset by any of the following events: ? power-up ? wrdi instruction execution ? wrsr instruction completion ? write instruction completion ? write protect ( w ) is driven low write disable (wrdi) sequence s w c d q instruction 1 0 234567 high-z v ih v il v ih v il v ih v il v ih v il r10ds0034ej0100 rev.1.00 page 11 of 20 feb. 25, 2013
r1ex25002asa00g/r1ex25004asa00g/R1EX25002ATA00G/r1ex25004ata00g read status register (rdsr): the read status register (rdsr) instruction allows the status register to be read. the status register may be read at any time, even while a write or write status register cycle is in progress. when on e of these cycles is in progress, it is recommended to check the write in progress (wip) bit before sending a new instruction to the device. it is also possible to read the status register continuously, as shown in the following figure. read status register (rdsr) sequence s w c d q status register out 01234567 0123456 77 8 9 10 11 12 13 14 15 high-z v ih v il v ih v il v ih v il v ih v il the status and control bits of th e status register are as follows: wip bit: the write in progress (wip) bit indicates whether th e memory is busy with a write or write status register cycle. when set to 1, such a cycl e is in progress. when reset to 0, no such cycles are in progress. wel bit: the write enable latch (wel) bit indicates the status of the internal write enable latch. when set to 1, the internal write enable latch is set. when set to 0, the inte rnal write enable latch is reset and no write or write status register instructions are accepted. bp1, bp0 bits: the block protect (bp1, bp0) bits are non-volatile. they define the size of the area to be software protected against write instructions. these bits are written w ith the write status register (wrsr) instruction. when one or both of the block protect (bp1, bp0) bits are set to 1, the relevant memory area (as defined in the status register format table) becomes protected against write (write) instructions. the block protect (bp1, bp0) bits can be written provided that the hardware protected mode has not been set. r10ds0034ej0100 rev.1.00 page 12 of 20 feb. 25, 2013
r1ex25002asa00g/r1ex25004asa00g/R1EX25002ATA00G/r1ex25004ata00g write status register (wrsr): the write status register (wrsr) instruction allows new valu es to be written to the status register. before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded and executed, the device sets th e write enable latch(wel). the instruction sequence is shown in the following figure. the write status register (wrsr) instruction has no effect on b6, b5, b4, b1 and b0 of the status register. b6, b5 and b4 ar e always read as 0. chip select ( s ) must be driven high after the rising edge of serial clock (c) that latches in the eighth bit of the data byte, and before the next rising edge of serial clock (c). otherwise, the write status register (wrsr) instruc tion is not executed. as soon as chip select ( s ) is driven high, the self-timed write status regist er cycle (whose duration is t w ) is initiated. while the write status register cycle is in progress, the status register may still be read to check th e value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed write status regi ster cycle, and is 0 when it is completed. when the cycle is completed, write enable latch(wel) is reset. the write status register (wrsr) inst ruction allows the user to change the values of the block protect (bp1, bp0) bits, to define the size of the area that is to be treated as read-only, as defined in the status register format table. the contents of block protect (bp1, bp0) b its are frozen at their current values ju st before the start of the execution of the write status register (wrsr) instructio n. the new, updated values take effect at the moment of completion of the execution of write status register (wrsr) instruction. write status register (wrsr) sequence s w c d q status register in msb 01234567 01234567 8 9 10 11 12 13 14 15 high-z v ih v il v ih v il v ih v il v ih v il r10ds0034ej0100 rev.1.00 page 13 of 20 feb. 25, 2013
r1ex25002asa00g/r1ex25004asa00g/R1EX25002ATA00G/r1ex25004ata00g read from memory array (read): as shown in the following figure, to send th is instruction to the device, chip select ( s ) is first driven low. the bits of the instruction byte and the address bytes are then shifted in, on serial data input (d). the addresses are loaded into an internal address register, and the byte of data at that addr ess is shifted out, on serial data output (q). the most significant address (a8) should be sent as fifth bit in the instruction byte. if chip select ( s ) continues to be driven low, the internal address re gister is automatically incr emented, and the byte of data at the new address is shifted out. when the highest address is reached, the address counter rolls over to zero, allo wing the read cycle to be continued indefinitely. the whole memory can, therefore, be read with a single read instruction. the read cycle is terminated by driving chip select ( s ) high. the rising edge of the chip select ( s ) signal can occur at any time during the cycle. the addressed first byte can be any byte within any page. the instruction is not accepted, and is not executed, if a write cycle is currently in progress. read from memory array (read) sequence s w c d q 8-bit address data out 2 data out 1 01234567 a0a1a2a3a5a6a7 a8 8 9 10 12 13 14 15 16 17 18 19 20 21 22 23 high-z v ih v il v ih v il v ih v il v ih v il 012 3 4 5 6 77 instruction note: 1. depending on the memory size, as shown in the following table, the most significant address bits are don?t care. address range bits device r1ex25004a r1ex25002a address bits a8 to a0 a7 to a0 note: 1. a8 is don?t care on the r1ex25002a. r10ds0034ej0100 rev.1.00 page 14 of 20 feb. 25, 2013
r1ex25002asa00g/r1ex25004asa00g/R1EX25002ATA00G/r1ex25004ata00g write to memory array (write): as shown in the following figure, to send th is instruction to the device, chip select ( s ) is first driven low. the bits of the instruction byte, address byte, and at least one data by te are then shifted in, on serial data input (d). the instruction is terminated by driving chip select ( s ) high at a byte boundary of the input data. in the case of the following figure, this occurs after the eighth bit of the data byte has been latched in, indicating that the instruction is being used to write a single byte. the self-timed write cycle starts, and continues for a period t wc (as specified in ac characteristics). at the end of the cycle, the write in progress (wip) bit is reset to 0. if, though, chip select ( s ) continues to be driven low, as shown in the following figure, the next byte of the input data is shifted in, so that more than a single byte, starting from the given address towards the end of the same page, can be written in a single internal write cycle. each time a new data byte is shifted in, the least significant b its of the internal address count er are incremented. if the number of data bytes sent to the device exceeds the page boundary, the internal address counter rolls over to the beginning of the page, and the previous data there are overwritten with the incoming data. (the page size of these device is 32 bytes). the instruction is not accepted, and is no t executed, under the following conditions: ? if the write enable latch (wel) bit has not been set to 1 (by executing a write enable instruction just before) ? if a write cycle is already in progress ? if the addressed page is in the region protected by the block protect (bp1 and bp0) bits. ? if write protect ( w ) is low byte write (write) sequence (1 byte) s w c d q 8-bit address data byte 1 01234567 0123 a5a6a7 8 9 10 12 13 14 15 16 17 18 19 20 21 22 23 high-z v ih v il v ih v il v ih v il v ih v il 4 5 6 7 a0 a1 a2 a3 instruction a8 note: 1. depending on the memory size, as shown in addr ess range bits table, the most significant address bit is don?t care. r10ds0034ej0100 rev.1.00 page 15 of 20 feb. 25, 2013
r1ex25002asa00g/r1ex25004asa00g/R1EX25002ATA00G/r1ex25004ata00g byte write (write) sequence (page) s w c d q 8-bit address data byte 1 01234567 0123 a5a6a7 8 9 10 12 13 14 15 16 17 18 19 20 21 22 23 high-z v ih v il v ih v il v ih v il v ih v il 4 5 6 7 a0 a1 a2 a3 instruction s w c d q data byte 3 data byte n 24 25 26 27 28 29 30 31 7 32 33 34 35 36 37 38 39 high-z v ih v il v ih v il v ih v il 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 6 5 4 3 2 1 0 data byte 2 a8 note: 1. depending on the memory size, as shown in addr ess range bits table, the most significant address bit is don?t care. r10ds0034ej0100 rev.1.00 page 16 of 20 feb. 25, 2013
r1ex25002asa00g/r1ex25004asa00g/R1EX25002ATA00G/r1ex25004ata00g data protect the block protect bits (bp1, bp0) define the area of memory that is protected against the execution of write cycle, as summarized in the following table. when write protect ( w ) is driven low, write to memory array (write) and write status register (wrsr) are disabled, and wel bit is reset. write protected block size status register bits array addresses protected bp1 bp0 protected blocks r1ex25004a r1ex25002a 0 0 none none none 0 1 upper quarter 180h ? 1ffh c0h ? ffh 1 0 upper half 100h ? 1ffh 80h ? ffh 1 1 whole memory 000h ? 1ffh 00h ? ffh hold condition the hold ( hold ) signal is used to pause any serial communicatio ns with the device without resetting the clocking sequence. during the hold condition, the serial data output (q) is high im pedance, and serial data input (d) and serial clock (c) are don?t care. to enter the hold condition, the device mu st be selected, with chip select ( s ) low. normally, the device is kept selected, for the whole duration of the hold condition. deselecting the device while it is in the hold condition, has the effect of resetting the state of the device, and this mechanism can be used if it is required to reset any processes that had been in progress. the hold condition starts when the hold ( hold ) signal is driven low at the same time as serial clock (c) already being low (as shown in the following figure). the hold condition ends when the hold ( hold ) signal is driven high at the same time as serial clock (c) already being low. the following figure also shows what happens if the rising and falling edges are not timed to coincide with serial clock (c) being low. hold condition activation c hold hold status hold status r10ds0034ej0100 rev.1.00 page 17 of 20 feb. 25, 2013
r1ex25002asa00g/r1ex25004asa00g/R1EX25002ATA00G/r1ex25004ata00g r10ds0034ej0100 rev.1.00 page 18 of 20 feb. 25, 2013 notes data protection at v cc on/off when v cc is turned on or off, noise on s inputs generated by external circuits (c pu, etc) may act as a trigger and turn the eeprom to unintentional program mode. to prevent this unintentional programming, this eeprom have a power on reset function. be careful of the noti ces described below in order for the power on reset function to operate correctly. ? s should be fixed to v cc during v cc on/off. low to high or high to low transition during v cc on/off may cause the trigger for the unintentional programming. ? v cc should be turned on/o ff after the eeprom is placed in a standby state. ? v cc should be turned on from the ground level (v ss ) in order for the eeprom not to enter the unintentional programming mode. ? v cc turn on rate should be slower than 2 ? s/v. ? when wrsr or write instruction is executed before v cc turns off, v cc should be turned off after waiting write cycle time (t w ). power source noise countermeasures in order to suppress power-source-noise which causes malfunction of the device, it is recommended to put 0.1uf bypass-capacitor (such as a monolithic ceramic capacitor wh ich has good high-frequency characteristics) between v cc and v ss , and shorten the wiring leng th between the capacitor and v cc /v ss terminals as much as possible.
r1ex25002asa00g/r1ex25004asa00g/R1EX25002ATA00G/r1ex25004ata00g package dimensions r1ex25002asa00g/r1ex25004asa00g (prsp00 08df-b / previous code: fp-8dbv) prsp0008df-b p-sop8-3.9x4.89-1.27 a l e c b d e a b c x y h z l 2 1 1 e 1 mass[typ.] 0.08g 4.89 1.06 0.25 0 8 6.02 0.15 0.20 0.25 0.45 0.102 0.14 0.254 3.90 0.406 0.60 0.889 1.73 reference symbol dimension in millimeters min nom max previous code jeita package code renesas code fp-8dbv 5.15 1 a p 0.35 0.40 6.20 5.84 1.27 0.10 0.69 index mark e 1 y xm p *3 *2 *1 f 4 85 d e h a z b p terminal cross section ( ni/pd/au plating ) b c detail f 1 1 l l a note) 1. dimensions"*1 (nom)"and"*2" do not include mold flash. 2. dimension"*3"does not include trim offset. e r10ds0034ej0100 rev.1.00 page 19 of 20 feb. 25, 2013
r1ex25002asa00g/r1ex25004asa00g/R1EX25002ATA00G/r1ex25004ata00g R1EX25002ATA00G/r1ex25004ata00g (ptsp 0008jc-b / previous code: ttp-8dav) ptsp0008jc-b p-tssop8-4.4x3-0.65 a l e c b d e a b c x y h z l 2 1 1 e 1 mass[typ.] 0.034g 3.00 1.00 0.13 0 8 6.40 0.10 0.15 0.20 0.25 0.03 0.07 0.10 4.40 0.40 0.50 0.60 1.10 reference symbol dimension in millimeters min nom max previous code jeita package code renesas code ttp-8dav 3.30 1 a p 0.15 0.20 6.60 6.20 0.65 0.10 0.805 *1 85 e *2 index mark 14 *3 p mx y f a d e h z b detail f 1 1 a l l p terminal cross section ( ni/pd/au plating ) c b note) 1. dimensions"*1 (nom)"and"*2" do not include mold flash. 2. dimension"*3"does not include trim offset. e r10ds0034ej0100 rev.1.00 page 20 of 20 feb. 25, 2013
all trademarks and registered trademarks are t he property of their respective owners. c - 1 revision history r1ex2500 2asa00g/r1ex25004asa00g R1EX25002ATA00G/r1ex25004ata00g data sheet description rev. date page summary 0.01 nov. 08, 2010 initial issue 1.00 oct. 02, 2012 ? dlete preliminary 1 data retention: change 10 years to 20 years. 2 ordering information: change #s0 to #u0. addition of halogen free. 3 block diagram: addition of voltage detector. memory cell characteristics: data retention: change 10 years to 20 years. 4 addition dc characteristics i sb =0.5 ? a(typ)@3.6v, i cc1 =0.2ma(typ)@3.6v, , i cc2 =1.0ma(typ)@3.6v 18 addition these items for notes (power source noise countermeasures)
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